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Actually the Intel 386 chip could use 48 bit addressing using the Segment Descriptor Table. Apparently nobody wanted to write the OS to take advantage of it. 4 GB seemed like a huge space then. Plus MS got the guys from DEC who did VMS, which used a flat 32 bit address space, to write NT. It was just easier to let them apply their experience rather than complicating things.

According to Microsoft it's possible for a 32-bit system to access more than 4 GB of physical memory providing PAE (physical address extension) is explicitly enabled.

With PAE, the operating system moves from two-level linear address translation to three-level address translation. Instead of a linear address being split into three separate fields for indexing into memory tables, it is split into four separate fields: a 2-bit field, two 9-bit fields, and a 12-bit field that corresponds to the page size implemented by Intel architecture (4 KB). The size of page table entries (PTEs) and page directory entries (PDEs) in PAE mode is increased from 32 to 64 bits. The additional bits allow an operating system PTE or PDE to reference physical memory above 4 GB.

K4sum1 wrote: ↑21 Dec 2022, 18:04 Wait is the 386 a 48 bit CPU?

It is in the sense that the register width is 32-bits, the integer math is limited to 32-bits (64-bit result), and it has a 32-bit instruction set. 48-bit addressing refers to how the PC handles memory.

luk3Z wrote: ↑21 Dec 2022, 17:38

Actually the Intel 386 chip could use 48 bit addressing using the Segment Descriptor Table. Apparently nobody wanted to write the OS to take advantage of it. 4 GB seemed like a huge space then. Plus MS got the guys from DEC who did VMS, which used a flat 32 bit address space, to write NT. It was just easier to let them apply their experience rather than complicating things.

According to Microsoft it's possible for a 32-bit system to access more than 4 GB of physical memory providing PAE (physical address extension) is explicitly enabled.

With PAE, the operating system moves from two-level linear address translation to three-level address translation. Instead of a linear address being split into three separate fields for indexing into memory tables, it is split into four separate fields: a 2-bit field, two 9-bit fields, and a 12-bit field that corresponds to the page size implemented by Intel architecture (4 KB). The size of page table entries (PTEs) and page directory entries (PDEs) in PAE mode is increased from 32 to 64 bits. The additional bits allow an operating system PTE or PDE to reference physical memory above 4 GB.

https://www.sevenforums.com/hardware-devices/193323-possible-use-full-4gb-ram-win7-x86.html
https://www.raymond.cc/blog/make-windows-7-and-vista-32-bit-x86-support-more-than-4gb-memory/
https://learn.microsoft.com/en-us/windows/win32/memory/physical-address-extension?redirectedfrom=MSDN
https://github.com/wj32/PatchPae2